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FIFOs, RAMs, and ROMs

Unlike random-access memories (RAMs) and read-only memories (ROMs), a FIFO does not require an address to access data. Another difference between a FIFO and a RAM or ROM is data retention: in a RAM or ROM, data at a particular address remains unchanged until another value is written into the memory, and reading a data value does not change or erase the value from the memory. In a FIFO, data written into the memory is retained until it is read out; and once the data word is read out, it no longer exists in the memory and cannot be accessed again. (The exceptions to this rule are FIFOs that have a retransmit feature; retransmission allows for a segment of a FIFO’s memory to be read many times, although the data is written into the FIFO only once.)

Further, due to the nature of their data retention, FIFOs, unlike RAMs or ROMs, have a state of “data fullness” associated with them. A FIFO can be empty, partially filled, or full, and it requires additional signal lines, or flags, to indicate the state of its memory content. The number of data words a FIFO can store before it is full depends on its size; like RAMs and ROMs, FIFOs are manufactured with different memory organizations (see table).

FIFO applications

Because of a FIFO’s unique attributes, it is useful in some applications where a RAM or ROM is cumbersome. The general class of applications best suited to FIFOs are those that deal with serial streams of data. Consider, for instance, a peripheral such as a video camera or network connection sending serial data over a bus to a processor. The source of the data (e.g., the camera or network hub) may provide short bursts of data at high speed, too fast for the data bus. To prevent data loss, a buffer must store the incoming words until the data bus is ready to service the transfer to the processor. If you used RAMs to implement the buffer, you would need additional circuitry, such as a direct-memory access (DMA) controller, to supply and increment the RAM’s read and write addresses as the data from the peripheral is being stored and later forwarded onto the data bus. You can avoid the extra design effort and expense by using a FIFO. That is, since a FIFO has no addressing requirements and provides data at the read port in the same order the data was presented at the write port, no additional circuitry is needed to implement a store-and-forward buffer.

The store-and-forward buffer example indicates another application particularly well suited to FIFOs. In the example, data is written into the FIFO by a high-speed data source and read out onto a lower-speed data bus. The FIFO converts the data rate from a high speed to a lower speed. The example demonstrates that a FIFO does not require a specific relationship between its input and output data rates. This means that a FIFO can serve as a link between two asynchronous interfaces.

Error recovery is an application in which the retransmit feature is useful. Suppose network packets are sent through the FIFO then across a very long cable to a receiver. Because there is a possibility of data corruption on the long cable, you should use a FIFO with retransmit to hold the transmitted data until the packet’s recipient confirms a successful transmission; if data is corrupted, the retransmit feature will resend the packet until it is received error-free.

Asynchronous FIFOs

FIFO read and write port interfaces are available in either asynchronous or synchronous versions. Asynchronous FIFOs use read and write pulses to access the memory. That is, when data is presented at the right time with respect to a write pulse, the data is written into memory; similarly, a read pulse pulls data from memory. The width of the read and write pulses must meet certain requirements for the FIFO to operate correctly; i.e., the write pulse width requirement defines the minimum write cycle, and the read pulse width requirement defines the minimum read cycle. The read access time defines the latency (delay) from the time a read is requested until the data is presented at the read port.
Asynchronous. In an asynchronous FIFO, a write pulse places the data present on the write port into the memory. Data must be present for one setup time before the deasserting edge of the write pulse (the high-to-low transition for an active-high pulse, and the low-to-high transition for an active-low pulse). A read pulse pulls data from the memory onto the read port. Data appears on the read port after one access time from the asserting edge of the read pulse. Note that as the read and write enables approach one another, the falling and rising edges of the empty flag also approach one another, decreasing the empty flag width.

The data-state flag signals for asynchronous FIFOs are updated one access time after completion of the write or read affecting the state of the memory, and indicate whether or not a write or read is possible. If the FIFO is empty, reads are ignored; a full FIFO ignores writes. Further, by monitoring the FIFO’s empty and full flags, a circuit using a FIFO can determine whether or not a read or write will be valid. For an asynchronous FIFO, the monitoring circuits must be able to handle arbitrarily small flag pulse widths, which may result when all flags are updated by both the read and the write pulses.

For example, if reads and writes occur very close together at an empty or full boundarycondition, the size of the empty or full flag could approach that of a glitch. As the read- and write-enables approach one another, the falling and rising edges of the empty flag also approach one another, decreasing the width of the empty flag.

In most applications, the empty and full flags are used to gate the read and write pulses, respectively, so very narrow empty or full flags are not significant. Nevertheless, any asynchronous FIFO application that relies on monitoring the empty or full flags should be designed to handle an arbitrarily small flag width.

Synchronous FIFOs

Synchronous FIFOs use read and write clocks and enable lines to access memory. The clocks can be in burst mode or free running and do not need to have any specific relationship with one another (i.e., the read and write clocks do not have to be synchronized).

Supplying an active write-enable one setup time prior to the rising edge of the write clock lets data be written into memory; similarly, reading data from memory requires the read-enable to be active one setup time prior to the rising edge of the read clock. The frequency of the write clock determines the fastest rate that data can be placed into the memory, while the frequency of the read clock determines the fastest rate that data can be pulled from the memory.
Synchronous. Synchronous FIFOs use read and write clocks and enable lines to access memory: supplying an active write-enable one setup time prior to the rising edge of the write clock lets data be written into memory; similarly, reading data from memory requires the read-enable be active one setup time prior to the rising edge of the read clock. The read clock, asserted when read enable is active, pulls the desired data from the memory and places it onto the read port. The frequency of the write clock determines the fastest rate that data can be placed into the memory, while the frequency of the read clock determines the fastest rate that data can be pulled from the memory.

As in asynchronous FIFOs, the data-state flag signals in synchronous FIFOs are updated one access time after completion of the write or read affecting the state of the memory. Synchronous FIFO flag updates differ from asynchronous FIFO flag updates, however, in that the pulse width of the flags has a guaranteed width based on the period of the read or write clocks. This is possible because the empty and full flags are latched internally, by the read and write clocks, respectively. So, no matter how closely together reads and writes occur, the state flags will always be valid for an entire clock cycle. This means that the state flags in a synchronous FIFO can be monitored by external circuits in which there is no need to handle arbitrarily small pulse widths.

Width expansion

Some applications may require a width or depth unavailable in a standard FIFO. To accommodate such designs, you can group FIFOs to increase the data word width or the memory depth, or both.

Width expansion involves using multiple FIFOs to emulate a single FIFO with a larger data-word width. For example, you can use two FIFOs, each with an 8K depth and an 18-bit word width (8K x 18), to create a FIFO with an 8K depth and a 36-bit word width (8K x 36). For many asynchronous and synchronous FIFOs, width expansion is simply a matter of operating multiple FIFOs in parallel, extending the data bus over the various devices, and driving one version of the read and write signals to all the parts.

A FIFO is a two-port memory based on dual-ported RAM cells. One port is used for writing data into the memory, while the other port is used for reading data out. A memory location can be written to and read from simultaneously, and a FIFO’s first-in/first-out architecture, or queue, defines the method for storing and retrieving data from memory: data is written into a FIFO one value at a time, and it is read from the device in the same order as it was written.

While a RAM must perform write and read operations sequentially, a FIFO can do them simultaneously. Thus, a FIFO has twice the throughput of a conventional RAM. What, then, is the maximum throughput frequency of a single FIFO in terms of its standalone operating frequency and its fallthrough time (the time needed to update the pointers to the RAM)?

The minimum throughput period (t_MIN) corresponding to the standalone period (data access time, t_A) and the fallthrough time (t_F) is, tmin = t_F + t_A. In terms of frequency, 1/f_MAX = t_F + 1/f_A, from which f_MAX = 1/(t_F + 1/f_A). Here, f_MAX is the FIFO’s maximum throughput frequency and f_A is the maximum standalone operating frequency.

Note that if the fallthrough time can be made zero, then f_MAX = f_A. A modern RAM-based architecture (i.e., one using a dual-ported RAM cell and pointers to address the RAM) essentially accomplishes this by reducing the fallthrough time to a very small value—which is why today’s FIFOs are referred to as zero-fallthrough-time FIFOs.

When its shift-in and shift-out signals are derived from independent frequency sources, the FIFO is operating asynchronously. In this mode, the relationship between the output-ready signal and the output system clock is not known, either with respect to frequency or with respect to phase. However, when the shift-in and shift-out signals are derived from a common frequency source or clock—so there is a precise, known relationship between them—the FIFO is by definition operating in the synchronous mode.

The three “goodness attributes” of FIFOs are the same as for RAMs—wider, deeper, faster. And just as the registered SRAM replaced the non-registered SRAM as processor speeds increased, the synchronous (clocked) FIFO is replacing the asynchronous FIFO. Indeed, because of their significant advantages over asynchronous FIFOs, synchronous FIFOs should be your choice for new designs. Their key advantages are as follow:

• Registered interfaces at the input and output provide the simplest and fastest FIFO interfacing—all signals are synchronized to the rising edges of the read or write system clocks, which run continuously and are applied directly to the FIFO;

• Read and write operations are easily manipulated by external, synchronous read and write state machines, which in turn are controlled by the read and write system clocks, respectively; and because the flags are internally synchronized to their respective clocks, external synchronizers are no longer needed;

• Read and write operations are controlled by enables, thereby eliminating any need for externally-generated read and write strobes; because the enable signals are sampled only during the rising edge of the clock (rather than in response to a level), noise immunity is improved (a fundamental advantage of edge sensing over level sensing), increasing system reliability.

Memory inside. This diagram depicts the structure of a modern, third-generation FIFO. In contrast to an asynchronous FIFO, which uses input and output handshaking signals, this is a synchronous device that uses read and write enables, continuously running read and write clocks, and status flags synchronized to the clocks. The fundamental FIFO architecture remains, however: dual-ported RAM cells at the core, surrounded by the logic needed to operate the device—which in a clocked FIFO consists mainly of flag and pointer circuitry. The general class of applications best suited to FIFOs are those that deal with serial streams of data, as in interfacing systems operating at different data rates and store-and-forward buffers. Indeed, since they are designed to have equal read and write cycles and have no address lines, FIFOs are the ultimate, infinitely expandable buffer; if you need more storage, just put a deeper FIFO in the same socket. And since there does not need to be a specific relationship between a FIFO’s input and output data rates, a FIFO can serve as a link between two asynchronous interfaces.

A first-in/first-out memory, or FIFO, is a memory device having two ports, one port for writing data into the memory, and one port for reading data out. Often called a queue, the first-in/first-out architecture defines the method for storing and retrieving data: that is, data is written into a FIFO one value at a time and read out in the same order.

Atmel® Corporation (NASDAQ: ATML) commented today that its financial guidance remains unchanged, and that the Company is executing on its restructuring plan to bring costs down and return the Company to profitability.

George Perlegos, President and Chief Executive Officer, stated, “We believe Atmel’s business is improving, as evidenced by the 14% sequential increase in second quarter revenues to $315 million, from $276 million in the first quarter of 2002. “Also, our financial position remains strong,” continued Perlegos. “Cash and equivalents totaled over $440 million at June 30, and our estimated EBITDA totaled $26 million for the second quarter, which is approximately double the level of the previous quarter.

“As we stated on the quarterly conference call last week, we have made a great deal of progress in the restructuring program to date, such as a reduction of approximately 1500 in headcount, and a $97 million reduction in operating expenses since the first quarter of 2001. Also we are continuing to take the appropriate steps to best position the Company for the upturn, such as the recently announced closure of Fab 8 in Irving, Texas.

Perlegos concluded, “We remain tightly focused on achieving our expense reduction goals by completing the Company-wide migration to more cost-effective technology processes such as 0.18 micron, closing or idling factories until the capacity is needed, and eventually closing some of our older facilities.”

Management believes these cost reduction measures should be completed over the next several quarters.

Atmel® Corporation (NASDAQ: ATML) today announced the introduction of a new family of products targeted for playing back images stored in flash cards and projecting them to a variety of display devices such as analog and digital TVs, digital cameras, LCD panels, projectors, etc. The first product in this line, AT76C112 has the ability to read images and video clips stored in flash cards, decompress them, and display them on the target display system. It supports SD^TM (Secure Digital), MMC^TM (MultiMedia Card), Memorystick®, CompactFlash®, SSFDC (Solid State Floppy Disk Card), and Atmel DataFlash® cards. Samples and software libraries are available now, evaluation boards will be available beginning of September. Production is now ramping up in support of several digital TV and multimedia projector manufacturers who are expected to announce end products this year.

AT76C112, which is the first of a family of products, is the most highly integrated flash card playback device in the market today. It requires fewer support chips than any other competitive product currently available. Based on an on-chip embedded ARM7® processor that controls the entire device, AT76C112 provides many hardware features, including compression/decompression engines, interfaces for all Flash cards, and system interfaces such as full speed USB and UART, as well as digital video output.

The device can be used in a variety of applications ranging from multimedia play back device, to flash card reader-assessor for PC applications.

Atmel’s Director of Multimedia Products, Tassos Markas remarked, “This technology enables consumers to view their pictures at a much higher resolution compared with traditional paper. Also, it can do it in a much more relaxed, user-friendly setting. With the rapid growth of digital still camera market and the high volume of digital imaging content, we expect that this new line of products will allow Atmel to grow our digital still camera IC business.”

Low-cost STK 594 Daughter Board Plugs into STK500

SAN JOSE, CA, September 3, 2002 . . . Atmel® Corporation (NASDAQ: ATML) announced today the availability of the STK 594 a low-cost add-on board that supports the FPSLIC^TM Product Family. Atmel’s AVR®-based FPSLIC components integrate a 20+ MIPS 8-bit AVR microcontrollwith a 5,000 to 40,000 gate FPGA, up to 36 K-bytes of SRAM, and peripherals. FPSLIC devices provide programmable logic and an AVR microcontroller on a single chip

The STK594 add-on board plugs directly into an AVR STK500 development board, creating a low cost FPSLIC development environment. Atmel’s FPSLIC devices offer designers a single chip solution with the additional memory and programmable logic. The STK594 development kit offers these designers a low cost and easy way to develop FPSLIC designs using the AVR development environment. Since FPSLIC code executes from on-chip SRAM, the AVR microcontroller performance is 20 or more MIPS.

The STK 594 includes the FPSLIC daughter board, Atmel’s System Designer co-verification, code- development, and EDA tool suite. The HDL Planner tool in System Designer automates the generation of the FPGA design, so embedded designers who are not familiar with a hardware description language (HDL) can quickly and easily create the FPGA portion of the design. System Designer’s co-verification back plane supports the simultaneous debugging of the processor code during the FPGA simulation.

According to Saroj Pathak, Atmel’s Programmable SLI Product Line Director, “Frequently, system designers find they need to add custom peripherals or additional logic to their MCU-based designs. However, the addition of an external FPGA or CPLD increases cost, board real estate, power consumption and design complexity. Adding external logic usually means that the embedded designer must learn how to use a hardware description language (HDL) or bring in a HDL designer – – lengthening the design cycle.

“The System Designer tool suite is very friendly to code developers. It integrates the code development and FPGA design tools in a co-verification environment that automates the generation of syntactically correct Verilog or VHDL from a library of over 50 point-and-click logic and memory functions selected by the designer. Embedded system designers who have no knowledge of hardware description languages can create the FPGA portion of the FPSLIC design quickly and easily with these tools,” Pathak concluded.

Atmel’s STK594 FPSLIC development kit is available now, priced at $149. The STK500 AVR Development Kit is available with a list price of $79.00

SAN JOSE CA September 17, 2002 . . . Atmel® Corporation (Nasdaq: ATML) announced today that it has started shipping its Low Pin Count (LPC) family of Flash memories. The AT49LL080 (8-Megabit) is designed to interface directly with the LPC bus used by chipsets from AMD^TM, Via^TM, SiS®, and others and supply the BIOS information on the PC motherboard.

The devices have uniform 64-Kbyte sectors and feature automated byte-program and sector-erase operations. Two configurable interfaces are supported: (1) Low Pin Count mode for in-system operation, and (2) Address/Address Multiplexed (A/A Mux) mode to accelerate memory array programming during manufacturing. The devices are offered in industry standard 40-lead TSOP and 32-lead PLCC surface mount packages.

“Atmel is excited about entering this new market for Flash memories.” stated Anup Sidhu, Director, Flash memory marketing. “We have been a primary supplier of conventional EPROM and Flash memories for PC BIOS applications for over 15 years, and our customers have recently started asking for LPC products. In addition to the AT49LL080 we will be introducing 4 Mbit and 2 Mbit LPC family members later this year as Atmel ramps its presence in this market.”

Pricing for the AT49LL080 is $3.50 in 10KU quantities.

Grenoble, France – September 26th, 2002. . . Atmel® Corporation announced today that it has awarded a distribution agreement in France to IMASYS for Atmel’s CCD Camera lines. IMASYS will source Atmel’s AVIIVA^TM M2 linescan range (0.5, 1-2-4 Kpixels high speed), CAMELIA^TM areascan family (resolution up to 8 Mpixels) and the recently announce AVIIVA^TM C2 monoline color camera family.

Christophe Robinet, Camera Marketing Manager for Atmel, said, “With their offer of a large range of vision solutions, many years of experience and high quality of service, they will add significant value to the customer relationships Atmel already has in France.”

About IMASYS
Founded in 1991, IMASYS is a highly technical French Company, independent and innovative, specialized in image processing since its creation. This indisputable success is based on our know- how and a thorough offering of high technology products providing solutions at all stages of the digital image processing chain. OEMs, integrators, manufacturers and searchers, working in the various fields of vision and image processing, rely on our skills in all industrial and research domains. For further information on IMASYS, go to our website at www.imasys.fr

IMASYS propose a complete products and services in France covering Video cameras, optics, lightings, electronic devices for machine vision; image processing device systems and frame grabber; software and image processing libraries and development platforms and machine vision systems.

AVIIVA C2 a high-speed, high-performance color single CCD camera and AKYLA a tri-CCD color camera target a variety of demanding industrial and color scanning applications

GRENOBLE FRANCE October 7, 2002. . . Atmel® Corporation (Nasdaq: ATML) announced today the availability of AT71C2LV and AT71C2CL, which make up AVIIVA^TM C2, a new member of the AVIIVA family of high-speed, high performance Line scan CCD Cameras. Additionally, the introduction of Atmel’s AT71MD represents a brand new family of tri-CCD color cameras called AKYLA^TM. Drawing on its advanced expertise in CCD design, technology and camera production, Atmel offers outstanding signal to noise ratios, and increased responsiveness compared with traditional CCD cameras. The AVIIVA product family has been built on a new user friendly concept comprising of three key design factors: versatility, accuracy and ease of implementation for applications such as web inspection to document scanning and from surface inspection to metrology.

The AVIIVA C2 incorporates a 4 K pixel sensor with a 10 micron meter pixel size and a RGB color pattern in a 56 mm wide casing, camera mounting holes, a versatile camera attachment and the ability to fix a heatsink on any side of the camera. The camera can operate up to 60 Mpixels/sec in 12 bits and offer a very competitive color scanning solution. Additionnal flexiblity is offered to the end-user via programmable settings alongside features such as data rate selection, trigger mode, antiblooming and exposure control functions with no lag effects.

The AKYLA family features 1 K and 2 K pixel sensors with a 10 micron meter pixel size targeting the most demanding color scanning applications with high color fidelity. The camera can operate up to 3×30 Mpixels/sec in 10 bits.

Both cameras are designed to offer excellent signal to noise performance.

The AVIIVA C2 and the AKYLA Line Scan families supports Camera Link^TM , the Automated Imaging Association’s new serial interface for the machine vision industry. With Camera Link, the system designer can access all data, synchronisation and total camera control with a unique and standard cable . The AVIIVA and ALKYLA Line Scan family also includes a parallel LVDS (Low Voltage Differential Signaling) version, which allows the use of longer cable. These cameras are in full production.

About Atmel
Founded in 1984, Atmel Corporation is headquartered in San Jose, California with manufacturing facilities in North America and Europe. Atmel designs, manufactures and markets worldwide, advanced logic, mixed-signal, nonvolatile memory and RF semiconductors. Atmel is also a leading provider of system-level integration semiconductor solutions using CMOS, BiCMOS, SiGe, and high-voltage BCDMOS process technologies.

© Atmel Corporation 2002. All rights reserved. Atmel, the Atmel logo and combinations thereof are registered trademarks and others contained herein, are trademarks of Atmel Corporation.

AVIIVA^TM is a trademark of Atmel Grenoble S.A. AKYLA? is a trademark of Atmel Grenoble S.A. CameraLink^TM is a trademark of the AIA ( Automated Imaging Association) Terms and product names in this document may be the trademarks of others.