Fifo Memory

FIFOs, RAMs, and ROMs

Unlike random-access memories (RAMs) and read-only memories (ROMs), a FIFO does not require an address to access data. Another difference between a FIFO and a RAM or ROM is data retention: in a RAM or ROM, data at a particular address remains unchanged until another value is written into the memory, and reading a data value does not change or erase the value from the memory. In a FIFO, data written into the memory is retained until it is read out; and once the data word is read out, it no longer exists in the memory and cannot be accessed again. (The exceptions to this rule are FIFOs that have a retransmit feature; retransmission allows for a segment of a FIFO’s memory to be read many times, although the data is written into the FIFO only once.)

Further, due to the nature of their data retention, FIFOs, unlike RAMs or ROMs, have a state of “data fullness” associated with them. A FIFO can be empty, partially filled, or full, and it requires additional signal lines, or flags, to indicate the state of its memory content. The number of data words a FIFO can store before it is full depends on its size; like RAMs and ROMs, FIFOs are manufactured with different memory organizations (see table).

FIFO applications

Because of a FIFO’s unique attributes, it is useful in some applications where a RAM or ROM is cumbersome. The general class of applications best suited to FIFOs are those that deal with serial streams of data. Consider, for instance, a peripheral such as a video camera or network connection sending serial data over a bus to a processor. The source of the data (e.g., the camera or network hub) may provide short bursts of data at high speed, too fast for the data bus. To prevent data loss, a buffer must store the incoming words until the data bus is ready to service the transfer to the processor. If you used RAMs to implement the buffer, you would need additional circuitry, such as a direct-memory access (DMA) controller, to supply and increment the RAM’s read and write addresses as the data from the peripheral is being stored and later forwarded onto the data bus. You can avoid the extra design effort and expense by using a FIFO. That is, since a FIFO has no addressing requirements and provides data at the read port in the same order the data was presented at the write port, no additional circuitry is needed to implement a store-and-forward buffer.

The store-and-forward buffer example indicates another application particularly well suited to FIFOs. In the example, data is written into the FIFO by a high-speed data source and read out onto a lower-speed data bus. The FIFO converts the data rate from a high speed to a lower speed. The example demonstrates that a FIFO does not require a specific relationship between its input and output data rates. This means that a FIFO can serve as a link between two asynchronous interfaces.

Error recovery is an application in which the retransmit feature is useful. Suppose network packets are sent through the FIFO then across a very long cable to a receiver. Because there is a possibility of data corruption on the long cable, you should use a FIFO with retransmit to hold the transmitted data until the packet’s recipient confirms a successful transmission; if data is corrupted, the retransmit feature will resend the packet until it is received error-free.

Asynchronous FIFOs

FIFO read and write port interfaces are available in either asynchronous or synchronous versions. Asynchronous FIFOs use read and write pulses to access the memory. That is, when data is presented at the right time with respect to a write pulse, the data is written into memory; similarly, a read pulse pulls data from memory. The width of the read and write pulses must meet certain requirements for the FIFO to operate correctly; i.e., the write pulse width requirement defines the minimum write cycle, and the read pulse width requirement defines the minimum read cycle. The read access time defines the latency (delay) from the time a read is requested until the data is presented at the read port.
Asynchronous. In an asynchronous FIFO, a write pulse places the data present on the write port into the memory. Data must be present for one setup time before the deasserting edge of the write pulse (the high-to-low transition for an active-high pulse, and the low-to-high transition for an active-low pulse). A read pulse pulls data from the memory onto the read port. Data appears on the read port after one access time from the asserting edge of the read pulse. Note that as the read and write enables approach one another, the falling and rising edges of the empty flag also approach one another, decreasing the empty flag width.

The data-state flag signals for asynchronous FIFOs are updated one access time after completion of the write or read affecting the state of the memory, and indicate whether or not a write or read is possible. If the FIFO is empty, reads are ignored; a full FIFO ignores writes. Further, by monitoring the FIFO’s empty and full flags, a circuit using a FIFO can determine whether or not a read or write will be valid. For an asynchronous FIFO, the monitoring circuits must be able to handle arbitrarily small flag pulse widths, which may result when all flags are updated by both the read and the write pulses.

For example, if reads and writes occur very close together at an empty or full boundarycondition, the size of the empty or full flag could approach that of a glitch. As the read- and write-enables approach one another, the falling and rising edges of the empty flag also approach one another, decreasing the width of the empty flag.

In most applications, the empty and full flags are used to gate the read and write pulses, respectively, so very narrow empty or full flags are not significant. Nevertheless, any asynchronous FIFO application that relies on monitoring the empty or full flags should be designed to handle an arbitrarily small flag width.

Synchronous FIFOs

Synchronous FIFOs use read and write clocks and enable lines to access memory. The clocks can be in burst mode or free running and do not need to have any specific relationship with one another (i.e., the read and write clocks do not have to be synchronized).

Supplying an active write-enable one setup time prior to the rising edge of the write clock lets data be written into memory; similarly, reading data from memory requires the read-enable to be active one setup time prior to the rising edge of the read clock. The frequency of the write clock determines the fastest rate that data can be placed into the memory, while the frequency of the read clock determines the fastest rate that data can be pulled from the memory.
Synchronous. Synchronous FIFOs use read and write clocks and enable lines to access memory: supplying an active write-enable one setup time prior to the rising edge of the write clock lets data be written into memory; similarly, reading data from memory requires the read-enable be active one setup time prior to the rising edge of the read clock. The read clock, asserted when read enable is active, pulls the desired data from the memory and places it onto the read port. The frequency of the write clock determines the fastest rate that data can be placed into the memory, while the frequency of the read clock determines the fastest rate that data can be pulled from the memory.

As in asynchronous FIFOs, the data-state flag signals in synchronous FIFOs are updated one access time after completion of the write or read affecting the state of the memory. Synchronous FIFO flag updates differ from asynchronous FIFO flag updates, however, in that the pulse width of the flags has a guaranteed width based on the period of the read or write clocks. This is possible because the empty and full flags are latched internally, by the read and write clocks, respectively. So, no matter how closely together reads and writes occur, the state flags will always be valid for an entire clock cycle. This means that the state flags in a synchronous FIFO can be monitored by external circuits in which there is no need to handle arbitrarily small pulse widths.

Width expansion

Some applications may require a width or depth unavailable in a standard FIFO. To accommodate such designs, you can group FIFOs to increase the data word width or the memory depth, or both.

Width expansion involves using multiple FIFOs to emulate a single FIFO with a larger data-word width. For example, you can use two FIFOs, each with an 8K depth and an 18-bit word width (8K x 18), to create a FIFO with an 8K depth and a 36-bit word width (8K x 36). For many asynchronous and synchronous FIFOs, width expansion is simply a matter of operating multiple FIFOs in parallel, extending the data bus over the various devices, and driving one version of the read and write signals to all the parts.