A FIFO is a two-port memory based on dual-ported RAM cells. One port is used for writing data into the memory, while the other port is used for reading data out. A memory location can be written to and read from simultaneously, and a FIFO’s first-in/first-out architecture, or queue, defines the method for storing and retrieving data from memory: data is written into a FIFO one value at a time, and it is read from the device in the same order as it was written.
While a RAM must perform write and read operations sequentially, a FIFO can do them simultaneously. Thus, a FIFO has twice the throughput of a conventional RAM. What, then, is the maximum throughput frequency of a single FIFO in terms of its standalone operating frequency and its fallthrough time (the time needed to update the pointers to the RAM)?
The minimum throughput period (tMIN) corresponding to the standalone period (data access time, tA) and the fallthrough time (tF) is, tmin = tF + tA. In terms of frequency, 1/fMAX = tF + 1/fA, from which fMAX = 1/(tF + 1/fA). Here, fMAX is the FIFO’s maximum throughput frequency and fA is the maximum standalone operating frequency.
Note that if the fallthrough time can be made zero, then fMAX = fA. A modern RAM-based architecture (i.e., one using a dual-ported RAM cell and pointers to address the RAM) essentially accomplishes this by reducing the fallthrough time to a very small value—which is why today’s FIFOs are referred to as zero-fallthrough-time FIFOs.
When its shift-in and shift-out signals are derived from independent frequency sources, the FIFO is operating asynchronously. In this mode, the relationship between the output-ready signal and the output system clock is not known, either with respect to frequency or with respect to phase. However, when the shift-in and shift-out signals are derived from a common frequency source or clock—so there is a precise, known relationship between them—the FIFO is by definition operating in the synchronous mode.
The three “goodness attributes” of FIFOs are the same as for RAMs—wider, deeper, faster. And just as the registered SRAM replaced the non-registered SRAM as processor speeds increased, the synchronous (clocked) FIFO is replacing the asynchronous FIFO. Indeed, because of their significant advantages over asynchronous FIFOs, synchronous FIFOs should be your choice for new designs. Their key advantages are as follow:
• Registered interfaces at the input and output provide the simplest and fastest FIFO interfacing—all signals are synchronized to the rising edges of the read or write system clocks, which run continuously and are applied directly to the FIFO;
• Read and write operations are easily manipulated by external, synchronous read and write state machines, which in turn are controlled by the read and write system clocks, respectively; and because the flags are internally synchronized to their respective clocks, external synchronizers are no longer needed;
• Read and write operations are controlled by enables, thereby eliminating any need for externally-generated read and write strobes; because the enable signals are sampled only during the rising edge of the clock (rather than in response to a level), noise immunity is improved (a fundamental advantage of edge sensing over level sensing), increasing system reliability.
Memory inside. This diagram depicts the structure of a modern, third-generation FIFO. In contrast to an asynchronous FIFO, which uses input and output handshaking signals, this is a synchronous device that uses read and write enables, continuously running read and write clocks, and status flags synchronized to the clocks. The fundamental FIFO architecture remains, however: dual-ported RAM cells at the core, surrounded by the logic needed to operate the device—which in a clocked FIFO consists mainly of flag and pointer circuitry. The general class of applications best suited to FIFOs are those that deal with serial streams of data, as in interfacing systems operating at different data rates and store-and-forward buffers. Indeed, since they are designed to have equal read and write cycles and have no address lines, FIFOs are the ultimate, infinitely expandable buffer; if you need more storage, just put a deeper FIFO in the same socket. And since there does not need to be a specific relationship between a FIFO’s input and output data rates, a FIFO can serve as a link between two asynchronous interfaces.
A first-in/first-out memory, or FIFO, is a memory device having two ports, one port for writing data into the memory, and one port for reading data out. Often called a queue, the first-in/first-out architecture defines the method for storing and retrieving data: that is, data is written into a FIFO one value at a time and read out in the same order.
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